An automatic cell pattern generation system for CMOS transistor-pair array LSI

In an automatic layout design system for masterslice or gate array LSI, a cell library must be provided in advance. Manual preparation of such a cell library requires a considerable amount of design effort and turnaround time. In this paper, an automatic cell pattern generation algorithm and its program implementation for a CMOS transistor-pair array masterslice are presented. The cell pattern generation process consists of the transistor-pair extraction, transistor-pair placement and routing phases. The transistor-pair placement method is based on an iterative improvement algorithm for wiring congestion. For the wiring phase, Lee's maze routing algorithm is modified for application to polysilicon, diffusion and two aluminum layers. Furthermore, a new interconnection ordering algorithm is proposed and its effectiveness for attaining higher wireability is experimentally shown. Finally, it is shown that the proposed cell pattern generation system achieves a significant reduction of cell pattern design time compared to conventional manual design.

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