Concatenated polar codes under successive cancellation list (SCL) decoding have excellent error-correction performance. However, their expected error-detection capability becomes degraded, when we increase the list size of the SCL decoder in order to improve their error-correction performance. In this paper, we propose a configuration design scheme for the SCL decoder and a post-decoding validation check scheme in order to provide a better tradeoff between error-detection and error-correction performance. Firstly, a configuration of the SCL decoder is designed to improve its own error detection capability. Specifically, a part of dynamic frozen bits (also called parity-check bits) is used for path checking during SCL decoding rather than their original purpose of use, path pruning. Furthermore, the number of paths to be checked by the applied cyclic redundancy check (CRC) code is limited. Secondly, a new metric corresponding to the correlation between the received signal vector and the decoded one is presented to check the validity of the decoding result. These proposed schemes are analyzed to provide a proper configuration of the SCL decoder and determine a threshold for post-decoding validation check. Numerical results show that a better tradeoff between error correction and detection is achieved, compared with conventional schemes.