Gate level leakage minimisation at 90 nm technology

In the modern era of ultra large scale integration, miniaturisation with lowest possible power dissipation is considered as the most significant challenge and is of a prime concern. But power dissipation in modern semiconductor devices is of inverse in nature with respect to the scaling of device dimension. Smaller is the physical dimension of integrated component, greater is the percentage of static power in the form of different leakage currents. This gets even more pronounced at nano-scale regime. This issue demands in additional cooling arrangements for the device, which results in economy, design and space overhead. In order to resolve the issues to some extent, in this paper, we have proposed an idea that is useful for leakage reduction of basic logic gates. We have evaluated our idea with both of CMOS-based NAND and NOR gate. The gates have been chosen because of their universal capability to implement other logic functions. An approximate value of 90% and 88% saving in static power for NAND and NOR gate respectively was found in comparison to their normal counterpart. But the proposed approach suffers from an additional area and delay overhead.