This work presents an 8b two-step SAR ADC for GS/s single-channel operations. A recursive-weight DAC topology is proposed in the 2nd stage with minimized capacitors and simple control logic. A partially-dual-plate sampling technique is exploited to relax the restraints of comparators and reduce the total amount of capacitors. Prototyped in a 40-nm CMOS process, this ADC occupies only 22×75 µm2. With a 580 MHz input sampled at 1.1 GS/s, it exhibits a SNDR of 45 dB and a SFDR of 66 dB under 4.0 mW power consumption, leading to a FOMw of 25 fJ/conv.-step. The measured effective resolution bandwidth is larger than 3 GHz.