Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations

End-of-road map CMOS (<=10nm) technology is expected to display extreme random variability in device parameters, resulting in a very large spread in the speed of individual gates. Based on reasonable statistical estimates, virtually every large circuit in this environment can be expected to contain several extremely slow statistical outlier gates which will severely limit performance in synchronous designs. To address this challenge, gate level tuning techniques have recently been proposed [2] that can potentially speed up the slow gates to recover much of this lost performance. However, such tuning significantly increases power dissipation, and therefore must only be activated in the relative few performance limiting outlier gates. Consequently, application of such tuning techniques requires that the slow outlier gates be correctly diagnosed for proper tuning. This presents the challenging problem of diagnosing multiple delay faults in the circuit. In this paper we show how the performance tuning capability of the circuit can itself be exploited, in combination with scan delay tests, to address this problem. Our approach involves selectively tuning and speeding up subsets of suspect gates, and then uniquely identifying the slow outlier gates based on whether the tuning eliminates the slow path or not. We show that such an approach can correctly diagnose multiple slow gates in large circuits for successful performance tuning.

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