Top-down RSFQ logic design based on a binary decision diagram
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[1] Nobuyuki Yoshikawa,et al. A cell-based design approach for RSFQ circuits using a binary decision diagram , 1999 .
[2] Nobuyuki Yoshikawa,et al. A Cell-Based Design Approach for RSFQ Circuits , 1999 .
[3] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[4] E. S. Fang,et al. A Josephson integrated circuit simulator (JSIM) for superconductive electronics application , 1989 .
[5] Nobuyuki Yoshikawa,et al. Data-driven self-timed RSFQ demultiplexer , 1998 .
[6] A. Krasniewski,et al. Tools for the computer-aided design of multigigahertz superconducting digital circuits , 1999, IEEE Transactions on Applied Superconductivity.
[7] V. Semenov,et al. RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.
[8] Tadahiro Kuroda,et al. Overview of low-power ULSI circuit techniques , 1999 .
[9] Kris Gaj,et al. Functional modeling of RSFQ circuits using Verilog HDL , 1997, IEEE Transactions on Applied Superconductivity.