HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.

[1]  Larry Pileggi,et al.  IC Interconnect Analysis , 2002 .

[2]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[3]  Kwang-Ting Cheng,et al.  Analysis of performance impact caused by power supply noise in deep submicron devices , 1999, DAC '99.

[4]  Charlie Chung-Ping Chen,et al.  Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Rajendran Panda,et al.  Design and analysis of power distribution networks in PowerPC microprocessors , 1998, DAC.

[6]  Sani R. Nassif,et al.  Fast power grid simulation , 2000, Proceedings 37th Design Automation Conference.

[7]  Charlie Chung-Ping Chen,et al.  INDUCTWISE: inductance-wise interconnect simulator and extractor , 2002, ICCAD 2002.

[8]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Ibrahim N. Hajj,et al.  Estimation of maximum current envelope for power bus analysis and design , 1998, ISPD '98.

[10]  Roland W. Freund,et al.  Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.

[11]  Kwang-Ting Cheng,et al.  Vector generation for maximum instantaneous current through supply lines for CMOS circuits , 1997, DAC.

[12]  Shu-Park Chan,et al.  Analysis of linear networks and systems : a matrix-oriented approach with computer applications , 1972 .

[13]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Ronald A. Rohrer,et al.  Electronic Circuit and System Simulation Methods , 1994 .

[15]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2000, DAC.

[16]  Larry L. Biro,et al.  Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[17]  Janet Roveda,et al.  Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources , 2000, Proceedings 37th Design Automation Conference.

[18]  David D. Ling,et al.  Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip Design , 1997, Proceedings of the 34th Design Automation Conference.