An extemal-capacitor-less low-dropout regulator with less than −36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate

An external capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection ratio (PSRR) at all low-to-high frequencies was presented. The LDO was designed to have the dominant pole, ωD, at the gate of the pass-transistor, VG, to secure stability without an external capacitor, even when the load current was large. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, where the ripples copied from the supply are injected adaptively to the body-gate, the PSRR-hump of conventional LDOs with wd at Vg can be suppressed significantly. Since the ASRC continues to adjust the magnitude of the injecting ripples, the LDO of this work is able to maintain high PSRRs, irrespective of the amount of the load current, IL, or the dropout voltage, VDo. The proposed LDO was fabricated in a 65-nm CMOS process, and it had an input voltage of 1.2V. When having a 240-pF load capacitor, the measured PSRRs were less than −36dB at all frequencies from 10kHz to 1GHz, despite changes in Il and VDo. The active area was 0.087mm2 including the 240-pF load capacitor, and the total power consumption was 360μW.