An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits
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[1] Melvin A. Breuer,et al. BALLAST: a methodology for partial scan design , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[2] K. S. Kim,et al. Partial scan by use of empirical testability , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[3] S.M. Reddy,et al. On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[4] Chung Len Lee,et al. Partial reset and scan for flip-flops based on states requirement for test generation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[5] Parker,et al. Design for Testability—A Survey , 1982, IEEE Transactions on Computers.
[6] Dong Sam Ha,et al. A new method for partial scan design based on propagation and justification requirements of faults , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[7] Klaus D. Müller-Glaser,et al. On the selection of a partial scan path with respect to target faults , 1991, Proceedings of the European Conference on Design Automation..
[8] Janak H. Patel,et al. An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.
[9] Srimat T. Chakradhar,et al. Peripheral partitioning and tree decomposition for partial scan , 1998, Proceedings Eleventh International Conference on VLSI Design.
[10] Alberto L. Sangiovanni-Vincentelli,et al. An incomplete scan design approach to test generation for sequential machines , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[11] K.-T. Cheng,et al. A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.
[12] S. Davidson,et al. Sequential Circuit Test Generator (STG) benchmark results , 1989, IEEE International Symposium on Circuits and Systems,.
[13] V.D. Agrawal,et al. Designing circuits with partial scan , 1988, IEEE Design & Test of Computers.
[14] Vishwani D. Agrawal,et al. Pascant: a partial scan and test generation system , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.
[15] W.-T. Cheng,et al. The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[16] John Grason,et al. Digital Test Generation and Design for Testability , 1980, 17th Design Automation Conference.
[17] Thomas W. Williams,et al. Design for Testability - A Survey , 1982, IEEE Trans. Computers.
[18] Miron Abramovici,et al. A Cost-Based Approach to Partial Scan , 1993, 30th ACM/IEEE Design Automation Conference.
[19] Chung-Len Lee,et al. Identifying invalid states for sequential circuit test generation , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] S. Venkataraman,et al. Partial scan design based on circuit state information , 1996, 33rd Design Automation Conference Proceedings, 1996.
[21] Vishwani D. Agrawal,et al. An exact algorithm for selecting partial scan flip-flops , 1994, 31st Design Automation Conference.
[22] Toshinobu Ono. Selecting Partial Scan Flip-flops For Circuit Partitioning , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[23] Melvin A. Breuer,et al. Automatic Design for Testability Via Testability Measures , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[24] Miron Abramovici,et al. On combining design for testability techniques , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[25] Rabindra K. Roy,et al. The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.
[26] Janak H. Patel,et al. A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[27] Sungju Park,et al. A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination , 1992, Proceedings International Test Conference 1992.
[28] Michael S. Hsiao,et al. Partial scan selection based on dynamic reachability and observability information , 1998, Proceedings Eleventh International Conference on VLSI Design.
[29] Irith Pomeranz,et al. On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation , 1994, IEEE Trans. Computers.
[30] Vishwani D. Agrawal,et al. An economical scan design for sequential logic test generation , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[31] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[32] Shang-E Tai,et al. A three-stage partial scan design method using the sequential circuit flow graph , 1994, Proceedings of 7th International Conference on VLSI Design.
[33] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[34] William A. Rogers,et al. A test methodology for finite state machines using partial scan design , 1992, J. Electron. Test..
[35] D. G. Saab,et al. Partial reset: An inexpensive design for testability approach , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[36] Daniel G. Saab,et al. On selecting flip-flops for partial reset , 1993, Proceedings of IEEE International Test Conference - (ITC).
[37] Arno Kunzmann,et al. An analytical approach to the partial scan problem , 1990, J. Electron. Test..
[38] Sharad Malik,et al. Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications , 1994, 31st Design Automation Conference.
[39] Janak H. Patel,et al. A global algorithm for the partial scan design problem using circuit state information , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[40] Miron Abramovici,et al. Testability-based partial scan analysis , 1995, J. Electron. Test..