Increment/decrement/2's complement/priority encoder circuit for varying operand lengths

Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2's complement etc. This paper presents an architecture which can perform increment/decrement/2's complement/priority-encode operations on varying data lengths. A 32-bit implementation of the proposed multifunctional architecture is presented, which can operate on four 8-bit operands, two 16-bit operands or one 32-bit operand.

[1]  Martin Margala,et al.  Efficient addition circuits for Modular design of processors-in-memory , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Yu-Jen Huang,et al.  A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[3]  Ruby B. Lee.  Subword parallelism with MAX-2 , 1996, IEEE Micro.

[4]  Michael J. Schulte,et al.  Multiplier architectures for media processing , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[5]  Vojin G. Oklobdzija,et al.  Multiplexer based adder for media signal processing , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[6]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[7]  Stefania Perri,et al.  A high-speed energy-efficient 64-bit reconfigurable binary adder , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Chin-Long Wey,et al.  Design of reconfigurable array multipliers and multiplier-accumulators , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[9]  J. Fridman.  Sub-word parallelism in digital signal processing , 2000 .

[10]  Asim Al-Khalili,et al.  Multiplexer-based binary incrementer/decrementers , 2005, The 3rd International IEEE-NEWCAS Conference, 2005..

[11]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[12]  Jean-Luc Gaudiot,et al.  A Logarithmic Time Method for Two's Complementation , 2005, International Conference on Computational Science.

[13]  M.B. Srinivas,et al.  A novel high-speed binary and gray Incrementer/Decrementer for an address generation unit , 2007, 2007 International Conference on Industrial and Information Systems.

[14]  Chung-Hsun Huang,et al.  Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques , 2002 .

[15]  Stefania Perri,et al.  64-bit reconfigurable adder for low power media processing , 2002 .

[16]  Reza Hashemian,et al.  A new parallel technique for design of decrement/increment and two's complement circuits , 1991, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems.