Efficient Implementation of AES IP

The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estimation in FPGA implementation with Altera and Xilinx platforms are also presented. The hardware implementation results of the proposed architecture with Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation has less area cost as compared with previous relevant architecture. Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance

[1]  Hua Li,et al.  An efficient architecture for the AES mix columns operation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[2]  Shau-Yin Tseng,et al.  Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter , 2002, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors.

[3]  Ming-Chih Chen,et al.  Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Milos Drutarovský,et al.  InvMixColumn decomposition and multilevel resource sharing in AES implementations , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Keshab K. Parhi,et al.  High-speed VLSI architectures for the AES algorithm , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Cheng-Wen Wu,et al.  A high-throughput low-cost AES processor , 2003, IEEE Communications Magazine.

[7]  Joan Daemen,et al.  AES Proposal : Rijndael , 1998 .

[8]  Akashi Satoh,et al.  A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.