A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters

In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-/spl mu/m CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.

[1]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  Masao Nakaya,et al.  An 80-MHz 8-bit CMOS D/A converter , 1986 .

[3]  M. Vadipour,et al.  Gradient error cancellation and quadratic error reduction in unary and binary D/A converters , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[4]  Liang Jing,et al.  A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Michiel Steyaert,et al.  A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Yun-Che Wen,et al.  BIST structure for DAC testing , 1998 .

[7]  John W. Fattaruso,et al.  Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation , 1990 .

[8]  Soon-Jyh Chang,et al.  BIST scheme for DAC testing , 2002 .

[9]  Michel Steyaert,et al.  A 12-bit intrinsic accuracy high-speed CMOS DAC , 1998, IEEE J. Solid State Circuits.

[10]  Mohamad Sawan,et al.  On chip testing data converters using static parameters , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Bozena Kaminska,et al.  Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[12]  Klaas Bult,et al.  A 10b , 500-MSample / s CMOS DAC in 0 . 6 mm , 1999 .

[13]  Michiel Steyaert,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001 .

[14]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.

[15]  Randall L. Geiger,et al.  Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays , 2000 .

[16]  Walter Modell,et al.  CRC Handbook of Tables for Probability and Statistics , 1966 .

[17]  J. E. Franca,et al.  Error detection and analysis in self-testing data conversion systems employing charge-redistribution techniques , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[18]  A. Maeda,et al.  A 10-bit 70 MS/s CMOS D/A converter , 1990 .

[19]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[20]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[21]  Mohamad Sawan,et al.  New frequency-locked loop based on CMOS frequency-to-voltage converter: design and implementation , 2001 .

[22]  William H. Beyer,et al.  Handbook of Tables for Probability and Statistics , 1967 .

[23]  Yonghua Cong,et al.  A 1.5 V 14 b 100 MS/s self-calibrated DAC , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[24]  K. Cheng,et al.  A BIST scheme for on-chip ADC and DAC testing , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[25]  Randall L. Geiger,et al.  Formulation of INL and DNL yield estimation in current-steering D/A converters , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[26]  Michiel Steyaert,et al.  An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters , 2001 .