Hardware Implementation and Performance Evaluation of the HEVC Intra-predicted $$4\times 4$$4×4 Blocks Transforms

This paper presents a performance evaluation of the high efficiency video coding (HEVC) based exclusively on the discrete cosine transform DCT-II and compares it to the reference algorithm which uses with the DCT-II, a discrete sine transform (DST-VI) for $$4\times 4$$4×4 intra-predicted luminance blocks. Then, a modified version of DST-VI called “MDST-VI” is proposed and evaluated. Using the HEVC reference model HM-16.3 and the main profile, the test results show that the MDST-VI presents an interesting compromise between the DST-VI and the DCT-II. The former leads to the best rate-distortion results, the latter yields a quality mean decrease of 0.02 dB and a mean bit-rate increase of 0.47 %, while the MDST_VI reduces the previous figures to the tenth. In a second part, a FPGA implementation performance analysis of the three transforms indicates that the DCT-II and the MDST-VI outperform the DST-VI with a 55.27 and 41.35 % area reduction, 47.73 and 10.61 % energy saving, and 85.70 and 10.55 % throughput gain, respectively. The MDST-VI could well fulfill the requirements of present and next-generation mobile communication where high-throughput and low-powered hardware accelerators are highly desirable while ensuring the best quality and the lowest bit-rate.