Effective Data Transmission with UART on Kintex-7 FPGA

Fast data communication is the need of today’s generation. This is because of the advancements and growth of technologies. This research work is about the implementation and analysis of data communication of Universal Asynchronous Receiver Transmitter (UART) on Kintex-7 Field Programmable Gate Array (FPGA) at different clock periods. The implementation is done on the VIVADO tool and analysis of data communication for different clock time is done by timing summary option available on the VIVADO tool. It is observed that data communication takes place in UART when the clock period is 3ns or more than 3ns because for the data transfer Worst Negative Slack (WNS) and Worst Hold Slack (WHS) both must be positive and Total Hold Slack (THS) and Total Negative Slack (TNS) should be 0.000. If the clock period is less than 3ns no data transfer will take place.

[1]  Davide Anguita,et al.  Introduction to FPGA and HDL Design , 2019 .

[2]  Amanpreet Kaur,et al.  Low Power UART Design Using Different Nanometer Technology Based FPGA , 2018, 2018 8th International Conference on Communication Systems and Network Technologies (CSNT).

[3]  B. U. V. Prashanth,et al.  Design & implementation of floating point ALU on a FPGA processor , 2012, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET).

[4]  Ionel Petrescu,et al.  Digital Logic Introduction Using FPGAs , 2015 .

[5]  Amanpreet Kaur,et al.  Effect of Different Nano Meter Technology Based FPGA on Energy Efficient UART Design , 2018, 2018 8th International Conference on Communication Systems and Network Technologies (CSNT).

[6]  Naresh Grover,et al.  An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM , 2018 .

[7]  Kenneth S. Stevens,et al.  Qualifying Relative Timing Constraints for Asynchronous Circuits , 2016, 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

[8]  Bishwajeet Pandey,et al.  Stack memory implementation and analysis of timing constraint, power and memory using FPGA , 2017, 2017 9th International Conference on Computational Intelligence and Communication Networks (CICN).

[9]  M. Pattanaik,et al.  Clock gating based energy efficient ALU design and implementation on FPGA , 2013, 2013 International Conference on Energy Efficient Technologies for Sustainability.

[10]  Jon Frankle,et al.  Iterative and adaptive slack allocation for performance-driven layout and FPGA routing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  Bishwajeet Pandey,et al.  Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA , 2018 .