Critical dimension (CD) metrology is an important process step within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately tolerances of device electrical performance drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process and photomask quality. At the 65nm node the ITRS roadmap calls for sub-3nm photomask CD uniformity to support a sub-3nm wafer level CD uniformity. Meeting these targets has proven to be a challenge. What can be inferred from these specifications is that photomask level CD performance is the direct contributor to wafer level CD performance. With respect to phase shift masks, criteria such as phase and transmission control are also tightened with each technology node. A comprehensive study is presented supporting the use of photomask aerial image emulation CD metrology to predict wafer level Across Chip Linewidth Variation (ACLV). Using the aerial image can provide more accurate wafer level prediction because it inherently includes all contributors to image formation such as the physical CD, phase, transmission, sidewall angle, and other material properties. Aerial images from different photomask types were captured to provide across chip CD values. Aerial image measurements were completed using an AIMSTMfab193i with its through-pellicle data acquisition capability including the Global CDU MapTM software option for AIMSTM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CD data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using aerial image CD metrology.
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