The impact of SILC to data retention in sub-half-micron embedded EEPROMs

Abstract Stress-Induced-Leakage-Current (SILC) in sub-half-micron technology embedded EEPROM has been extensively studied by performing gate stress measurements on pre-conditioned EEPROM arrays. This paper reports that the SILC path is very localized; the SILC path can be turned “on” and “off” statistically independent on the electrical field, as shown by the experiments; the SILC caused Vt shift can be fitted into a power-law against the number of programming/erase cycles; the measured current-voltage characteristics of SILC can be well described with Poole-Frenkel model; and EEPROM retention time prediction can be made by extrapolating the gate stress data with fitted Poole-Frenkel parameters.