Poisson AERgenerator: Inter-Spike-Inte rvals Analysis

Address-Event-Representation (AER) is a pixels whosecodeoraddress wasonthebus.Inthis way, communication protocol fortransferring asynchronous events cells withthesameaddress intheemitter andreceiver chips between VLSIchips, originally developed forbio-inspired arevirtually connected withastream ofpulses. Thereceiver processing systems(forexample, imageprocessing). Such cellintegrates thepulses andreconstructs theoriginal low systems may consist ofa complicated hierarchical structurefrequency continuous-time waveform. Cells that aremore withmanychips thattransmit dataamongtheminrealtime, while performing someprocessing (for example, convolutions). active access thebusmorefrequently thanthose less active. Todevelop AER basedsystems forimageprocessing itisvery CHIPI CHIP2 convenient tohaveavailable somekindoftoolforgenerating /_ IDIGITAL AER streams fromon-computer stored images. Inthis paper 02 oD° we present a hardware methodforgenerating AER streams C withPoisson statistics inrealtimefroma sequence ofimages stored inacomputer's memory.We quantify thattheevents generated follow aPoisson distribution using theKolmogorov- Smirnov test. We havedeveloped aUSB-AERboard, basedon Figure 1:Rate-Coded AERinter-chip communication scheme. the XilinxSpartanII FPGA and the Cygnal8051 microcontroller, developed byourRTCAR grouphavebeen Transmitting thecelladdresses allows performing extra usedfortheanalysis.Tas1hgtecl drse lospromn xr