Effective diagnostics through interval unloads in a BIST environment

Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hardware overhead. Tester fail-data collection is based on a novel construct incorporated into the design-extensions of the standard test interface language (STIL). The implementation of the proposed method is presented and analyzed.

[1]  Paul H. Bardell,et al.  Self-Testing of Multichip Logic Modules , 1982, International Test Conference.

[2]  Vinod K. Agarwal,et al.  A diagnosis method using pseudo-random vectors without intermediate signatures , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  B. Koenemann LFSR-coded test patterns for scan designs , 1991 .

[4]  Vishwani D. Agrawal,et al.  A Tutorial on Built-In Self-Test, Part 2: Applications , 1993, IEEE Des. Test Comput..

[5]  Janusz Rajski,et al.  Automated synthesis of large phase shifters for built-in self-test , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Nur A. Touba,et al.  A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[7]  Thomas W. Williams,et al.  Design of compactors for signature-analyzers in built-in self-test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).