NBTI-aware adaptive minimum leakage vector selection using a linear programming approach

Due to the circuit aging effect, the minimum leakage vector (MLV) found by the traditional input vector control method may not obtain the optimal leakage power reduction result when the circuit begins to degrade. To solve this problem, we present an adaptive MLV selection strategy based on a linear programming approach. The method divides the total lifetime of the circuit into a succession of time intervals, and the MLV used in each interval is periodically updated according to the transistor's threshold voltage degradation so that the best overall power reduction result can be achieved. Experimental results on various benchmark circuits show the effectiveness of our method. An NBTI-aware adaptive minimum leakage vector selection method has been proposed.The impact of the NBTI effect on leakage power and MLV selection has been analyzed.SVR is used to build the model between threshold voltage change and leakage power.MLV is updated according to aging condition by ILP approach to reduce leakage power.The impact of MLV update on NBTI-induced path delay increase has been analyzed.

[1]  Mehdi Baradaran Tahoori,et al.  Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  James Myers,et al.  Active Mode Subclock Power Gating , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Bernhard Schölkopf,et al.  A tutorial on support vector regression , 2004, Stat. Comput..

[4]  Guilherme Flach,et al.  Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  J. Meindl,et al.  A physical alpha-power law MOSFET model , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[6]  Manisha Pattanaik,et al.  Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study , 2014, J. Circuits Syst. Comput..

[7]  F. Liu,et al.  A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[8]  Massoud Pedram,et al.  Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits , 2005, IEICE Trans. Electron..

[9]  Krishnendu Chakrabarty,et al.  Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Massoud Pedram,et al.  Leakage current reduction in CMOS VLSI circuits by input vector control , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Yu Wang,et al.  On the efficacy of input Vector Control to mitigate NBTI effects and leakage power , 2009, 2009 10th International Symposium on Quality Electronic Design.

[12]  James H. Stathis,et al.  The negative bias temperature instability in MOS devices: A review , 2006, Microelectron. Reliab..

[13]  Gang Qu,et al.  A combined gate replacement and input vector control approach for leakage current reduction , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Bo Yang,et al.  Optimized Circuit Failure Prediction for Aging: Practicality and Promise , 2008, 2008 IEEE International Test Conference.

[15]  Stephen P. Boyd,et al.  Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  James H. Stathis,et al.  Reliability of advanced high-k/metal-gate n-FET devices , 2010, Microelectron. Reliab..

[17]  R. Rao,et al.  A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits , 2003, ICCAD 2003.

[18]  James D. Meindl,et al.  A physical alpha-power law MOSFET model , 1999 .

[19]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[20]  D. M. H. Walker,et al.  A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations , 2008, Integr..

[22]  Ku He,et al.  Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation , 2011, IEEE Transactions on Dependable and Secure Computing.

[23]  Qiang Xu,et al.  Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  John P. Hayes,et al.  Exact and heuristic approaches to input vector control for leakage power reduction , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[25]  Sani R. Nassif,et al.  Full chip leakage estimation considering power supply and temperature variations , 2003, ISLPED '03.

[26]  Yu Cao,et al.  The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  Miodrag Potkonjak,et al.  Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[28]  Cody Hao Yu,et al.  Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Chih-Jen Lin,et al.  LIBSVM: A library for support vector machines , 2011, TIST.