A CMOS 510 K-transistor single-chip token-ring LAN controller (TRC) compatible with IEEE802.5 MAC protocol

The token-ring controller (TRC) consists of five functional blocks. they are a dedicated 16-b microprocessor which includes 11 K-word*20-b protocol firmware ROM, finite-state machines for real-time handling of frames, an 896-word*16-b dual-port RAM for frame buffer FIFOs and working memory (FIFO/RAM), a host processor bus interface, and a three-channel DMA controller which can follow list structure frame buffers. The TRC interprets and executes 16 types of commands and handles 23 types of media access control (MAC) frames. It can continuously receive more than 90% of incoming packets with 64-byte information length at 40 Mbit/s network speed. It is fabricated with double-metal-layer 1.2- mu m CMOS technology and integrates 510 K MOSFETs in a 14.49-mm*14.62-mm chip area. The maximum power consumption is 0.945 W at 8-MHz operating frequency and 5-V+or-5% power supply low-power systems but also for high-performance applications. >

[1]  C. Hull,et al.  An IEEE802.5 compatible LAN controller with on-chip ROM , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  W. Bux.  Local-Area Subnetworks: A Performance Comparison , 1981, IEEE Trans. Commun..

[3]  関根 優年,et al.  An Application on ASIC Design with Mixed - level Simulator FAL , 1987 .

[4]  P. Lou,et al.  A VLSI communication processor designed for testability , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  K. Tamaru,et al.  Design of a CMOS token ring LAN controller, TRC, compatible with IEEE802.5 MAC protocol , 1989, Symposium 1989 on VLSI Circuits.