Logic Meets Algebra: Compositional Timing Analysis for Synchronous Reactive Multithreading

The intuitionistic theory of the real interval [0, 1], known as Skolem-Godel-Dummet logic (SGD), generates a well-known Heyting algebra intermediate between intuitionistic and classical logic. Originally of purely mathematical interest, it has recently received attention in Computer Science, notably for its potential applications in concurrency theory. In this paper we show how the logical operators of SGD over the discrete frame \({\mathbb Z} _\infty \), extended by the additive group structure \(({\mathbb Z}, 0, +)\), provides an expressive and yet surprisingly economic calculus to specify the quantitative stabilisation behaviour of synchronous programs. This is both a new application of SGD and a new way of looking at the semantics of synchronous programming languages. We provide the first purely algebraic semantics of timed synchronous reactions which adapts Berry’s semantics for Esterel to work on general concurrent/sequential control-flow graphs. We illustrate the power of the algebra for the modular analysis of worst-case reaction time (WCRT) characteristics for time-predictable reactive processors with hardware-supported multi-threading.

[1]  Isabella Stilkerich,et al.  The Perfect Getaway , 2017, ACM Trans. Embed. Comput. Syst..

[2]  Stephen A. Edwards,et al.  Predictable programming on a precision timed architecture , 2008, CASES '08.

[3]  Michael Dummett,et al.  A propositional calculus with denumerable matrix , 1959, Journal of Symbolic Logic (JSL).

[4]  Xin Li,et al.  Multithreaded Reactive Programming—the Kiel Esterel Processor , 2012, IEEE Transactions on Computers.

[5]  Gérard Berry,et al.  The ESTEREL Synchronous Programming Language and its Mathematical Semantics , 1984, Seminar on Concurrency.

[6]  Partha S. Roop,et al.  Programming and Timing Analysis of Parallel Programs on Multicores , 2013, 2013 13th International Conference on Application of Concurrency to System Design.

[7]  Partha S. Roop,et al.  ILPc: A novel approach for scalable timing analysis of synchronous programs , 2013, 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[8]  Sander Stuijk,et al.  Worst-case Performance Analysis of Synchronous , 2010 .

[9]  Roopak Sinha,et al.  Efficient WCRT analysis of synchronous programs using reachability , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Michael Mendler,et al.  An Algebra of Synchronous Scheduling Interfaces , 2011, FIT.

[12]  Stephen A. Edwards,et al.  The Case for the Precision Timed (PRET) Machine , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[13]  Marian Boldt,et al.  Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing , 2008, EURASIP J. Embed. Syst..

[14]  Yuri Gureoich Intuitionistic Logic , 2008 .

[15]  Partha S. Roop,et al.  Compositional timing-aware semantics for synchronous programming , 2017, 2017 Forum on Specification and Design Languages (FDL).

[16]  Stephen A. Edwards,et al.  A disruptive computer design idea: Architectures with repeatable timing , 2009, 2009 IEEE International Conference on Computer Design.

[17]  Samarjit Chakraborty,et al.  Context-sensitive timing analysis of Esterel programs , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[18]  Yoichi Hirai,et al.  A Lambda Calculus for Gödel-Dummett Logic Capturing Waitfreedom , 2012, FLOPS.

[19]  Partha S. Roop,et al.  A Novel WCET Semantics of Synchronous Programs , 2016, FORMATS.

[20]  Samarjit Chakraborty,et al.  Performance debugging of Esterel specifications , 2008, CODES+ISSS '08.

[21]  Partha S. Roop,et al.  Tight WCRT analysis of synchronous C programs , 2009, CASES '09.

[22]  Michael Mendler,et al.  WCRT algebra and interfaces for esterel-style synchronous processing , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[23]  Sander Stuijk,et al.  Worst-case performance analysis of Synchronous Dataflow scenarios , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[24]  Jürgen Dingel,et al.  A survey of timed automata for the development of real-time systems , 2013, Comput. Sci. Rev..

[25]  Michael Mendler,et al.  Constructive Boolean circuits and the exactness of timed ternary simulation , 2012, Formal Methods Syst. Des..

[26]  Christian G. Fermüller,et al.  Parallel Dialogue Games and Hypersequents for Intermediate Logics , 2003, TABLEAUX.

[27]  Petr Hájek,et al.  Metamathematics of Fuzzy Logic , 1998, Trends in Logic.

[28]  Partha S. Roop,et al.  Timing Analysis of Synchronous Programs using WCRT Algebra , 2017, ACM Trans. Embed. Comput. Syst..

[29]  Pascal Raymond,et al.  Timing analysis enhancement for synchronous program , 2013, RTNS.

[30]  Martin Schoeberl,et al.  Time-Predictable Computer Architecture , 2009, EURASIP J. Embed. Syst..