Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)

A BIST-Assisted Timing-Tracking (BATT) scheme is proposed in this paper to facilitate robust read operation in an SRAM design without sacrificing any circuit performance at all. This scheme has very low area overhead since it uses commonly existing memory BIST circuit for tracking the worst-case silicon speed of the bitlines. It is also highly scalable and therefore suitable for an SRAM compiler that needs to support a wide range of different configurations. Measurement results of 8 manufactured chips of a 2 K-bit SRAM design using TSMC 0.18-mum CMOS technology demonstrate that it can indeed rescue one originally failing chip, while still warranting correct functionality of all the other seven chips, even under some injected variations in which conventional schemes may fail badly.

[1]  M. Yoshida,et al.  Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[2]  T. Nirschl,et al.  Yield and speed optimization of a latch-type voltage sense amplifier , 2004, IEEE Journal of Solid-State Circuits.

[3]  Shi-Yu Huang,et al.  X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs , 2008, IEEE Journal of Solid-State Circuits.

[4]  Ding-Ming Kwai,et al.  Measurement and characterization of 6T SRAM cell current , 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

[5]  K. Ishibashi,et al.  Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[6]  Bharadwaj Amrutur,et al.  A replica technique for wordline and sense control in low-power SRAM's , 1998, IEEE J. Solid State Circuits.

[7]  Tadahiro Kuroda,et al.  A bitline leakage compensation scheme for low-voltage SRAMs , 2001, IEEE J. Solid State Circuits.

[8]  George S. Nolas,et al.  Measurement and Characterization , 2001 .

[9]  H. Pilo,et al.  An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage , 2007, IEEE Journal of Solid-State Circuits.

[10]  K. Yamaguchi,et al.  A 0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[11]  M. Usami,et al.  A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).