A parallel integer programming approach to global routing

We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses at it core an existing integer programming (IP) formulation-both for routing each subproblem and for connecting them. Concurrent processing of the routing subproblems is desirable for effective parallelization. However, achieving no (or low) overflow global routing solutions without strong, coordinated algorithmic control is difficult. Our algorithm addresses this challenge via a patching phase that uses IP to connect partial routing solutions. Patching provides feedback to each routing subproblem in order to avoid overflow, later when attempting to connect them. The end result is a flexible and highly scalable distributed algorithm for global routing. The method is able to accept as input target runtimes for its various phases and produce high-quality solution within these limits. Computational results show that for a target runtime of 75 minutes, running on a computational grid of few hundred CPUs with 2GB memory, the algorithm generates higher quality solutions than competing methods in the open literature.

[1]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.

[2]  George B. Dantzig,et al.  Decomposition Principle for Linear Programs , 1960 .

[3]  C. Y. Lee.  An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[4]  Nils J. Nilsson,et al.  A Formal Basis for the Heuristic Determination of Minimum Cost Paths , 1968, IEEE Trans. Syst. Sci. Cybern..

[5]  Frank O. Hadlock,et al.  A shortest path algorithm for grid graphs , 1977, Networks.

[6]  Donald B. Johnson,et al.  Efficient Algorithms for Shortest Paths in Sparse Networks , 1977, J. ACM.

[7]  David S. Johnson,et al.  The Rectilinear Steiner Tree Problem is NP Complete , 1977, SIAM Journal of Applied Mathematics.

[8]  Michael Burstein,et al.  Hierarchical Wire Routing , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Ben Ting,et al.  Routing Techniques for Gate Array , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Man-Tak Shing,et al.  A decomposition algorithm for circuit routing , 1985 .

[11]  Miron Livny,et al.  Condor-a hunter of idle workstations , 1988, [1988] Proceedings. The 8th International Conference on Distributed.

[12]  Carl Sechen,et al.  A global router for sea-of-gates circuits , 1991, Proceedings of the European Conference on Design Automation..

[13]  Sung-Mo Kang,et al.  A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  A. Kahng,et al.  On optimal interconnections for VLSI , 1994 .

[15]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[16]  Xianlong Hong,et al.  TIGER: an efficient timing-driven global router for gate array and standard cell layout design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Jason Cong,et al.  Performance driven global routing for standard cell design , 1997, ISPD '97.

[18]  Jeff Linderoth,et al.  Topics in parallel integer optimization , 1998 .

[19]  Martin W. P. Savelsbergh,et al.  Branch-and-Price: Column Generation for Solving Huge Integer Programs , 1998, Oper. Res..

[20]  Global routing with crosstalk constraints , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  A. Balantekin.  Copenhagen , 1999, The Lancet.

[22]  Christoph Albrecht,et al.  Global routing by new approximation algorithms for multicommodityflow , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Ronald L. Rivest,et al.  Introduction to Algorithms, Second Edition , 2001 .

[24]  David Grove Jørgensen,et al.  A branch-and-price algorithm for switch-box routing , 2002, Networks.

[25]  Majid Sarrafzadeh,et al.  Pattern routing: use and theory for increasing predictability andavoiding coupling , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Raia Hadsell,et al.  Improved global routing through congestion estimation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[27]  Andrew B. Kahng,et al.  Highly scalable algorithms for rectilinear and octilinear Steiner trees , 2003, ASP-DAC '03.

[28]  Uri C. Weiser,et al.  Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.

[29]  Jinjun Xiong,et al.  Full-chip multilevel routing for power and signal integrity , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[30]  Jiang Hu,et al.  Coupling aware timing optimization and antenna avoidance in layer assignment , 2005, ISPD '05.

[31]  Yao-Wen Chang,et al.  Multilevel full-chip gridless routing considering optical proximity correction , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[32]  J. Desrosiers,et al.  A Primer in Column Generation , 2005 .

[33]  I-Min Liu,et al.  Post-placement voltage island generation under performance requirement , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[34]  Laleh Behjat,et al.  Fast integer linear programming based models for VLSI global routing , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[35]  Jason Cong,et al.  MARS-a multilevel full-chip gridless routing system , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[36]  D. Muller.  Optimizing Yield in Global Routing , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[37]  Yao-Wen Chang,et al.  A novel framework for multilevel full-chip gridless routing , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[38]  J. W. McPherson,et al.  Reliability challenges for 45nm and beyond , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[39]  Min Pan,et al.  FastRoute: A Step to Integrate Global Routing into Placement , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[40]  Yici Cai,et al.  Logic and Layout Aware Voltage Island Generation for Low Power Design , 2007, 2007 Asia and South Pacific Design Automation Conference.

[41]  David Z. Pan,et al.  BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[42]  Martin D. F. Wong,et al.  Archer: a history-driven global routing algorithm , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[43]  Kun Yuan,et al.  BoxRouter 2.0: architecture and implementation of a hybrid and robust global router , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[44]  Zhen Yang,et al.  An ILP based hierarchical global routing approach for VLSI ASIC design , 2007, Optim. Lett..

[45]  Muhammet Mustafa Ozdal,et al.  Archer: a history-driven global routing algorithm , 2007, ICCAD 2007.

[46]  Chris C. N. Chu,et al.  IPR: An Integrated Placement and Routing Algorithm , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[47]  Chris C. N. Chu,et al.  FastRoute 2.0: A High-quality and Efficient Global Router , 2007, 2007 Asia and South Pacific Design Automation Conference.

[48]  Yu Hu,et al.  DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm , 2007, 2007 Asia and South Pacific Design Automation Conference.

[49]  Ting-Chi Wang,et al.  A new global router for modern designs , 2008, 2008 Asia and South Pacific Design Automation Conference.

[50]  Anthony Vannelli,et al.  On routing in VLSI design and communication networks , 2008, Discret. Appl. Math..

[51]  Ting-Chi Wang,et al.  NTHU-Route 2.0: A fast and stable global router , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[52]  Michael D. Moffitt.  MaizeRouter: Engineering an Effective Global Router , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[53]  Jin Hu,et al.  Sidewinder: a scalable ILP-based router , 2008, SLIP '08.

[54]  Chris C. N. Chu,et al.  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[55]  Jarrod A. Roy,et al.  High-Performance Routing at the Nanometer Scale , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[56]  Yao-Wen Chang,et al.  High-performance global routing with fast overflow reduction , 2009, 2009 Asia and South Pacific Design Automation Conference.

[57]  Azadeh Davoodi,et al.  GRIP: Scalable 3D global routing using Integer Programming , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[58]  Yih-Lang Li,et al.  Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing , 2009, 2009 Asia and South Pacific Design Automation Conference.

[59]  Yue Xu,et al.  FastRoute 4.0: Global router with efficient via minimization , 2009, 2009 Asia and South Pacific Design Automation Conference.

[60]  Kun Yuan,et al.  BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability , 2009, TODE.

[61]  Michael D. Moffitt.  Global routing revisited , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[62]  Matthew J. Saltzman,et al.  Computational Experience with a Software Framework for Parallel Integer Programming , 2009, INFORMS J. Comput..

[63]  Yih-Lang Li,et al.  Multi-threaded collision-aware global routing with bounded-length maze routing , 2010, Design Automation Conference.

[64]  Azadeh Davoodi,et al.  A Pareto-algebraic framework for signal power optimization in global routing , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[65]  Jin Hu,et al.  Completing high-quality global routes , 2010, ISPD '10.

[66]  Mohamed I. Elmasry,et al.  A Power-Efficient Multipin ILP-Based Routing Technique , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[67]  Azadeh Davoodi,et al.  Power-driven global routing for multi-supply voltage domains , 2011, 2011 Design, Automation & Test in Europe.

[68]  Jarrod A. Roy,et al.  The ISPD-2011 routability-driven placement contest and benchmark suite , 2011, ISPD '11.

[69]  Azadeh Davoodi,et al.  GRIP: Global Routing via Integer Programming , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[70]  Yih-Lang Li,et al.  NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.