论文信息 - HCI/BTI coupled model: The path for accurate and predictive reliability simulations

HCI/BTI coupled model: The path for accurate and predictive reliability simulations

The standard qualification of CMOS Wafer Level Reliability by manufacturers consists in qualifying BTI mechanism from one side and HCI from another side independently. Their respective degradation are then assumed to be additive. Here, we study the interaction between both mechanisms through alternative stress sequences at device level and also in ring oscillators. Interaction formalism is proposed and implemented in Design-in-Reliability simulation framework. While two ageing mechanisms co-exist and are interacting, we consider the origin of mechanisms (non-conducting HCI, low-E HCI...) and quantify the weight of coupling. We also point out that without this interaction consideration in Design-in-Reliability simulation, results are significantly inaccurate and pessimistic. Finally, we present degradation results for a large amount of standard cell RO-based at package level, at different stress/time conditions and conclude that this feature of simulation is a must have in logic Design Platform characterization in order to avoid over-estimation of timing degradation.

[1] A. Bravaix,et al. Novel hot-carrier AC-DC design guidelines for advanced CMOS nodes , 2008, 2008 IEEE International Reliability Physics Symposium.

[2] M. Rafik,et al. Experimental analysis of defect nature and localization under hot-carrier and bias temperature damage in advanced CMOS nodes , 2013, 2013 IEEE International Integrated Reliability Workshop Final Report.

[3] Fernando Guarin,et al. Role of E-E scattering in the enhancement of channel hot carrier degradation of deep-submicron NMOSFETs at high V/sub GS/ conditions , 2001 .

[4] V. Huard. Two independent components modeling for Negative Bias Temperature Instability , 2010, 2010 IEEE International Reliability Physics Symposium.

[5] B. Kaczer,et al. Analytic modeling of the bias temperature instability using capture/emission time maps , 2011, 2011 International Electron Devices Meeting.

[6] Jordi Suñé,et al. Reliability Wearout Mechanisms in Advanced CMOS Technologies , 2009 .

[7] X. Federspiel,et al. Experimental characterization of the interactions between HCI, off-state and BTI degradation modes , 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.

[8] V. Huard,et al. Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature , 2009, 2009 IEEE International Reliability Physics Symposium.