X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector

This paper presents X-Press - a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed.

[1]  Minesh B. Amin,et al.  X-tolerant compression and application of scan-atpg patterns in a bist architecture , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Douglas R. Stinson.  Hill-Climbing Algerithms for the Construction of Combinatorial Designs , 1985 .

[3]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[4]  Janusz Rajski,et al.  Compactor independent direct diagnosis , 2004, 13th Asian Test Symposium.

[5]  Janak H. Patel,et al.  Application of Saluja-Karpovsky compactors to test responses with many unknowns , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[6]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Brion L. Keller,et al.  Extending OPMISR beyond 10x Scan Test Efficiency , 2002, IEEE Des. Test Comput..

[8]  Vivek Chickermane,et al.  Channel masking synthesis for efficient on-chip test compression , 2004, 2004 International Conferce on Test.

[9]  Irith Pomeranz,et al.  On Compacting Test Response Data Containing Unknown Values , 2003, ICCAD 2003.

[10]  Janusz Rajski,et al.  Modular compactor of test responses , 2006, 24th IEEE VLSI Test Symposium.

[11]  Sudhakar M. Reddy,et al.  On methods to improve location based logic diagnosis , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[12]  Wu-Tung Cheng,et al.  X-filter: filtering unknowns from compacted test responses , 2005, IEEE International Conference on Test, 2005..

[13]  Irith Pomeranz,et al.  On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[14]  Irith Pomeranz,et al.  On-chip compression of output responses with unknown values using lfsr reseeding , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[15]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Sudhakar M. Reddy,et al.  Convolutional compaction of test responses , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[18]  Bernd Becker,et al.  X-masking during logic BIST and its impact on defect coverage , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Alex Orailoglu,et al.  Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[20]  Hideo Fujiwara,et al.  Design and analysis of multiple weight linear compactors of responses containing unknown values , 2005, IEEE International Conference on Test, 2005..

[21]  Erik H. Volkerink,et al.  Response compaction with any number of unknowns using a new LFSR architecture , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[22]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[23]  Nilanjan Mukherjee,et al.  X-Press Compactor for 1000x Reduction of Test Data , 2006, 2006 IEEE International Test Conference.

[24]  Irith Pomeranz,et al.  On output response compression in the presence of unknown output values , 2002, DAC '02.

[25]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[26]  Janusz Rajski,et al.  Test response compactor with programmable selector , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[27]  L. Zhu,et al.  On sets of three mols with holes , 1985, Discret. Math..