Faster Adder Circuits for Inputs with Prescribed Arrival Times

We present an algorithm that computes a Boolean circuit for an AND-OR path (i.e., a formula of type $t_0 \land (t_1 \lor (t_2 \land ( \dots t_{m-1}) \dots )$ or $t_0 \lor (t_1 \land (t_2 \lor ( \dots t_{m-1}) \dots )$) with given arrival times for the input signals. Our objective function is delay, a generalization of depth. The maximum delay of the circuit we compute is $\log_2 W + \log_2 \log_2 m + \log_2 \log_2 \log_2 m + 5$, where $\lceil \log_2 W \rceil$ is a lower bound on the delay of any circuit depending on inputs $t_0, \dotsc, t_{m-1}$ with prescribed arrival times. Since the carry bit computation in adders reduces to evaluating AND-OR paths, up to a small additive constant, an adder with the same delay can be constructed. Our method yields the fastest circuits both for AND-OR paths and adders in terms of delay known so far.