Hardware Implementation of Fast Division Algorithm for GF(2m)

This paper proposes a fast division algorithm and architecture for GF(2m) using standard basis representation. The algorithm implemented is based on the binary extended GCD algorithm. We have shown that the computation speed of the proposed algorithm is significantly improved than the previous approach. The design can operate at a clock frequency of 80 MHz on Xilinx-VirtexII XC2V8000 FPGA device