Timing-driven placement based on partitioning with dynamic cut-net control
暂无分享,去创建一个
[1] Mark Horowitz,et al. Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Massoud Pedram,et al. Timing-driven bipartitioning with replication using iterative quadratic programming , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).
[3] Bernhard M. Riess,et al. SPEED: fast and efficient timing driven placement , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.
[4] Michael Burstein,et al. Timing Influenced Layout Design , 1985, 22nd ACM/IEEE Design Automation Conference.
[5] Andrew B. Kahng,et al. Partitioning-based standard-cell global placement with an exact objective , 1997, ISPD '97.
[6] Frank M. Johannes,et al. Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[7] Robert B. Hitchcock,et al. Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..
[8] Paul Penfield,et al. Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.
[9] Stuart E. Dreyfus,et al. An Appraisal of Some Shortest-Path Algorithms , 1969, Oper. Res..
[10] Kamal Chaudhary,et al. RITUAL: a performance driven placement algorithm , 1992 .
[11] Shashi Shekhar,et al. Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.
[12] S. Hakimi,et al. Globally optimal floorplanning for a layout problem , 1996 .
[13] Kai Wang,et al. Floorplan area optimization using network analogous approach , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.
[14] Vishwani D. Agrawal,et al. Chip Layout Optimization Using Critical Path Weighting , 1984, 21st Design Automation Conference Proceedings.
[15] Naveed A. Sherwani,et al. Algorithms for VLSI Physical Design Automation , 1999, Springer US.
[16] Sang-Yong Han,et al. Timing driven placement using complete path delays , 1990, 27th ACM/IEEE Design Automation Conference.
[17] Jürgen Koehl,et al. An analytic net weighting approach for performance optimization in circuit placement , 1991, 28th ACM/IEEE Design Automation Conference.
[18] Michael K. H. Fan,et al. On convex formulation of the floorplan area minimization problem , 1998, ISPD '98.
[19] Carl Sechen,et al. Timing Driven Placement for Large Standard Cell Circuits , 1995, 32nd Design Automation Conference.
[20] Ernest S. Kuh,et al. An Algorithm for Performance-Driven Placement of Cell-Based ICs , 1991 .
[21] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[22] Ernest S. Kuh,et al. Sequence-pair based placement method for hard/soft/pre-placed modules , 1998, ISPD '98.
[23] Kenneth Steiglitz,et al. Combinatorial Optimization: Algorithms and Complexity , 1981 .