A Framework for Modeling the Distributed Deployment of Synchronous Designs

Synchronous specifications are appealing in the design of large scale hardware and software systems because of their properties that facilitate verification and synthesis.When the target architecture is a distributed system, implementing a synchronous specification as a synchronous design may be inefficient in terms of both size (memory for software implementations or area for hardware implementations) and performance. A more elaborate implementation style where the basic synchronous paradigm is adapted to distributed architectures by introducing elements of asynchrony is, hence, highly desirable. Building on the tagged-signal model, we present a modeling for the distributed deployment of synchronous design. We offer a comparative exposition of various design approaches (synchronous, asynchronous, GALS, latency-insensitive, and synchronous programming) and we provide some insight on the role of signal absence in modeling synchronization in distributed concurrent systems. Finally, we compare two distinct methodologies, desynchronization and latency-insensitive design, and we elaborate on possible options to combine their results.

[1]  Benoît Caillaud,et al.  Hierarchic Normal Forms for Desynchronization , 1999 .

[2]  Stephen A. Edwards,et al.  The synchronous languages 12 years later , 2003, Proc. IEEE.

[3]  Edward A. Lee,et al.  A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Albert Benveniste,et al.  Compositionality in Dataflow Synchronous Languages: Specification and Distributed Code Generation , 2000, Inf. Comput..

[5]  Alberto L. Sangiovanni-Vincentelli,et al.  A methodology for correct-by-construction latency insensitive design , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[6]  Gérard Berry,et al.  The foundations of Esterel , 2000, Proof, Language, and Interaction.

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Benoît Caillaud,et al.  Concurrency in synchronous systems , 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

[9]  Benoît Caillaud,et al.  From Synchrony to Asynchrony , 1999, CONCUR.

[10]  P. Le Guernic,et al.  Hybrid dynamical systems theory and the Signal language , 1990 .

[11]  Pradip Bose,et al.  Synchronous interlocked pipelines , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[12]  Jean-Christophe Le Lann,et al.  POLYCHRONY for System Design , 2003, J. Circuits Syst. Comput..

[13]  Albert Benveniste,et al.  A Protocol for Loosely Time-Triggered Architectures , 2002, EMSOFT.

[14]  Albert Benveniste.  Some Synchronization Issues When Designing Embedded Systems from Components , 2001, EMSOFT.

[15]  Alberto L. Sangiovanni-Vincentelli,et al.  Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment , 2003, EMSOFT.

[16]  Pascal Raymond,et al.  The synchronous data flow programming language LUSTRE , 1991, Proc. IEEE.

[17]  Sandeep K. Shukla,et al.  Modeling and validating globally asynchronous design in synchronous frameworks , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[18]  Stephen A. Edwards,et al.  Design of embedded systems: formal models, validation, and synthesis , 1997, Proc. IEEE.

[19]  Luca P. Carloni.  A Formal Modeling Framework for Deploying Synchronous Designs on Distributed Architectures , 2003 .

[20]  Sandeep K. Shukla,et al.  Polychrony for formal refinement-checking in a system-level design methodology , 2003, Third International Conference on Application of Concurrency to System Design, 2003. Proceedings..

[21]  Alberto L. Sangiovanni-Vincentelli,et al.  Coping with Latency in SOC Design , 2002, IEEE Micro.

[22]  Luca P. Carloni,et al.  Latency-insensitive design , 2004 .

[23]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[24]  Alberto L. Sangiovanni-Vincentelli,et al.  Latency Insensitive Protocols , 1999, CAV.

[25]  Luciano Lavagno,et al.  A concurrent model for de-synchronization , 2003 .