Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation

[1]  Daniel G. Saab,et al.  CRIS: a test cultivation program for sequential VLSI circuits , 1992, ICCAD.

[2]  K.-T. Cheng,et al.  Fault simulation in a pipelined multiprocessor system , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[3]  Melvin A. Breuer.  A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits , 1971, IEEE Transactions on Computers.

[4]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[5]  Chen-Shang Lin,et al.  Parallel sequence fault simulation for synchronous sequential circuits , 1992, [1992] Proceedings The European Conference on Design Automation.

[6]  Janak H. Patel,et al.  Test generation in a parallel processing environment , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[7]  Ernst G. Ulrich,et al.  Concurrent simulation of nearly identical digital networks , 1973, Computer.

[8]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[9]  Janak H. Patel,et al.  Effectiveness of Heuristics Measures for Automatic Test Pattern Generation , 1986, 23rd ACM/IEEE Design Automation Conference.

[10]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[11]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..

[12]  Nikolaus Gouders,et al.  PARIS: a parallel pattern fault simulator for synchronous sequential circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[13]  Elizabeth M. Rudnick,et al.  Application of simple genetic algorithms to sequential circuit test generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[14]  William Gropp,et al.  Skjellum using mpi: portable parallel programming with the message-passing interface , 1994 .

[15]  Hideo Fujiwara,et al.  Optimal granularity of test generation in a distributed system , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Paolo Prinetto,et al.  Comparing topological, symbolic and GA-based ATPGs: an experimental approach , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[17]  Janak H. Patel,et al.  A parallel algorithm for fault simulation based on PROOFS , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[18]  John A. Chandy,et al.  A library-based approach to portable, parallel, object-oriented programming: interface, implementation, and application , 1994, Proceedings of Supercomputing '94.

[19]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[20]  Sunil B. Patil,et al.  A parallel branch and bound approach to test generation , 1990 .

[21]  Kwang-Ting Cheng,et al.  On the over-specification problem in sequential ATPG algorithms , 1992, DAC '92.

[22]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[23]  Glenn A. Kramer,et al.  Employing Massive Parallelism in Digital ATPG Algorithms , 1983, ITC.

[24]  Wu-Tung Cheng,et al.  Differential Fault Simulation - A Fast Method Using Minimal Memory , 1989, 26th ACM/IEEE Design Automation Conference.

[25]  Dong Sam Ha,et al.  HOPE: an efficient parallel fault simulator for synchronous sequential circuits , 1992, DAC '92.

[26]  Elizabeth Marie Rudnick.  Simulation-Based Techniques for Sequential Circuit Testing , 1994 .

[27]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[28]  Franc Brglez,et al.  Testability-Driven Random Test-Pattern Generation , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Daniel G. Saab,et al.  Portable parallel logic and fault simulation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[30]  Minesh B. Amin,et al.  Zamlog: a parallel algorithm for fault simulation based on Zambezi , 1996, Proceedings of International Conference on Computer Aided Design.

[31]  James H. Aylor,et al.  Results of a topologically partitioned parallel automatic test pattern generation system on a distributed-memory multiprocessor , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[32]  John S. Conery,et al.  The and/or process model for parallel interpretation of logic programs , 1983 .

[33]  Hans-Joachim Wunderlich.  Multiple distributions for biased random test patterns , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  Janak H. Patel,et al.  Test compaction for sequential circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  D. Krishnaswamy,et al.  Asynchronous parallel algorithms for test set partitioned fault simulation , 1997, Proceedings 11th Workshop on Parallel and Distributed Simulation.

[36]  Irith Pomeranz,et al.  On improving genetic optimization based test generation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[37]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[38]  Prithviraj Banerjee,et al.  Portable parallel test generation for sequential circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[39]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[40]  Thomas J. Snethen.  Simulator-oriented fault test generator , 1988, 25 years of DAC.

[41]  James H. Aylor,et al.  Parallel-processing techniques for automatic test pattern generation , 1992, Computer.

[42]  Michael S. Hsiao,et al.  Parallel genetic algorithms for simulation-based sequential circuit test generation , 1997, Proceedings Tenth International Conference on VLSI Design.

[43]  Irith Pomeranz,et al.  Classification of Faults in Synchronous Sequential Circuits , 1993, IEEE Trans. Computers.

[44]  Janak H. Patel,et al.  Parallel test generation for sequential circuits on general-purpose multiprocessors , 1991, 28th ACM/IEEE Design Automation Conference.

[45]  P. R. Menon,et al.  Special-purpose computer for logic simulation using distributed processing , 1982, The Bell System Technical Journal.

[46]  Michael H. Schulz,et al.  ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[47]  Sudhakar M. Reddy,et al.  A new test generation method for sequential circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[48]  Janak H. Patel,et al.  ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation , 1994, 31st Design Automation Conference.

[49]  Srinivas Patil,et al.  Parallel algorithms for test generation and fault simulation , 1991 .

[50]  Prithviraj Banerjee.  Parallel algorithms for VLSI computer-aided design , 1994 .

[51]  Elizabeth M. Rudnick,et al.  SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[52]  Prathima Agrawal,et al.  Sequential Circuit Test Generation on a Distributed System , 1993, 30th ACM/IEEE Design Automation Conference.

[53]  Ibrahim N. Hajj,et al.  Parallel-concurrent fault simulation , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[54]  F. Ozguner,et al.  Logic fault simulation on a vector hypercube multiprocessor , 1989, C3P.

[55]  Vipin Kumar,et al.  Automatic test pattern generation on parallel processors , 1991, Parallel Comput..

[56]  Kewal K. Saluja,et al.  On fault deletion problem in concurrent fault simulation for synchronous sequential circuits , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[57]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[58]  E. Cantu-Paz,et al.  The Gambler's Ruin Problem, Genetic Algorithms, and the Sizing of Populations , 1997, Evolutionary Computation.

[59]  Paolo Prinetto,et al.  A portable ATPG tool for parallel and distributed systems , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[60]  T. Chan.  Distributed automatic test pattern generation , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[61]  Prathima Agrawal,et al.  A directed search method for test generation using a concurrent simulator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[62]  Janak H. Patel,et al.  Theory and practice of sequential machine testing and testability , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[63]  Sundaram Seshu,et al.  On an Improved Diagnosis Program , 1965, IEEE Trans. Electron. Comput..

[64]  L. Darrell Whitley,et al.  Serial and Parallel Genetic Algorithms as Function Optimizers , 1993, ICGA.

[65]  Erik D. Goodman,et al.  Coarse-grain parallel genetic algorithms: categorization and new approach , 1994, Proceedings of 1994 6th IEEE Symposium on Parallel and Distributed Processing.

[66]  Paolo Prinetto,et al.  An automatic test pattern generator for large sequential circuits based on Genetic Algorithms , 1994, Proceedings., International Test Conference.

[67]  Reiko Tanese,et al.  Distributed Genetic Algorithms , 1989, ICGA.

[68]  Michael S. Hsiao,et al.  Alternating strategies for sequential circuit ATPG , 1996, Proceedings ED&TC European Design and Test Conference.

[69]  Michael S. Hsiao,et al.  Automatic test generation using genetically-engineered distinguishing sequences , 1996, Proceedings of 14th VLSI Test Symposium.

[70]  Janusz Rajski,et al.  Complexity of sequential ATPG , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[71]  Byungse So.  Time-efficient automatic test pattern generation systems , 1994 .

[72]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[73]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[74]  Lalit M. Patnaik,et al.  A Simulation-Based Test Generation Scheme Using Genetic Algorithms , 1993, The Sixth International Conference on VLSI Design.

[75]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.

[76]  Minesh B. Amin,et al.  ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator , 1996, Proceedings of 14th VLSI Test Symposium.

[77]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[78]  Elizabeth M. Rudnick,et al.  Overcoming the serial logic simulation bottleneck in parallel fault simulation , 1997, Proceedings Tenth International Conference on VLSI Design.

[79]  Soumitra Bose,et al.  Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[80]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.