论文信息 - Formal specification and simulation of instruction-level parallelism

Formal specification and simulation of instruction-level parallelism

In thhig paper we show how to formally specify and simulate the high-level instruction timing properties Of RISC/Superscalar instruction 8et processor8. we illustrrzte the technique wing a hypothetical proces8or that include8 many feature8 of commercial processors including delayed load8 and branches, interlocked floating-point instructions, and multiple instruction i88Ue. A8 our formalism we we SCCS, a synchronous proce8.r algebra designed for specifying timed, concurYWbt 8y8tem.8.

Jon Mauney | Edwin A. Harcourt | Todd A. Cook

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