High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality of fault simulation and test generation tools using nominal IC parameters, we studied BF detection as a function of the standard deviation of parameters: results show that a single test vector cannot ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing null escape probability is upper-bounded with respect to variations of parameters, as verified by Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for low frequency testing. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability.

[1]  Melvin A. Breuer,et al.  Process variations and their impact on circuit operation , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[2]  Bernd Becker,et al.  Resistive Bridge fault model evolution from conventional to ultra deep submicron , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[3]  R. Rodríguez-Montañés,et al.  Bridging defects resistance in the metal layer of a CMOS process , 1996, J. Electron. Test..

[4]  Kozo Kinoshita,et al.  Precise test generation for resistive bridging faults of CMOS combinational circuits , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[5]  Edward J. McCluskey,et al.  Quantitative analysis of very-low-voltage testing , 1996, Proceedings of 14th VLSI Test Symposium.

[6]  Michele Favalli,et al.  Bridging fault modeling and simulation for deep submicron CMOS ICs , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .