Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment

In this paper, we investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static+dynamic) in generic digital CMOS designs. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1-V processes. Rules-of-thumb are developed for optimal V/sub dd/'s and V/sub th/'s to be used in future designs. These models show the optimal second V/sub dd/ to be approximately half the nominal V/sub dd/ while the potential total power savings is significantly greater than previously anticipated (60%-65%). We describe the impact of level conversion delays and also demonstrate that the scaling properties of multivoltage systems are very good, particularly when considering impending device scaling advancements.

[1]  Robert M. Houle,et al.  FP 15.6: A 480MHz RISC Microprocessor in a 0.12pm Le, CMOS Technology with Copper Interconnects , 1998 .

[2]  Chenming Hu,et al.  Performance and Vdd scaling in deep submicrometer CMOS , 1998, IEEE J. Solid State Circuits.

[3]  K. Takeuchi,et al.  A new multiple transistor parameter design methodology for high speed low power SoCs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[4]  Himanshu Kaul,et al.  Future performance challenges in nanometer design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Tadahiro Kuroda,et al.  Utilizing surplus timing for power reduction , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[6]  Ankur Srivastava,et al.  On gate level power optimization using dual-supply voltages , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Yiu-Hing Chan,et al.  A 1.1 GHz first 64 b generation 2900 microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[8]  N. Rohrer.  A 480MHz RISC microprocessor in a 0.12μm Leff CMOS technology with copper interconnections , 1998 .

[9]  J. Petrovick,et al.  The circuit and physical design of the POWER4 microprocessor , 2002, IBM J. Res. Dev..

[10]  Takayasu Sakurai,et al.  Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[11]  Rajendran Panda,et al.  Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing , 1999, DAC '99.

[12]  M. Sachdev,et al.  Dual supply voltage clocking for 5 GHz 130 nm integer execution core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[13]  Sarma B. K. Vrudhula,et al.  Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[15]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[16]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[17]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[18]  D. Kramer,et al.  A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[19]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[20]  J. Tschanz,et al.  A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[21]  H. Arakida,et al.  A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[22]  Kimiyoshi Usami,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1998 .