Research note Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits

Key building blocks ‐ simple ternary inverter, positive ternary inverter and negative ternary inverter have been designed for operation at a low voltage ‐1 V in 2 lm, n-well standard CMOS process and simulated in SPICE3 for use in the design of ternary logic circuits. The back-gate bias method has been used in conjunction with the width/ channel (W/L) ratio of MOSFETs to generate the desired dc voltage transfer characteristics and transition region adjustment around midway between high and low logic levels. ” 2000 Elsevier Science Ltd. All rights reserved.

[1]  C. Tomovich,et al.  MOSIS - A gateway to silicon , 1988, IEEE Circuits and Devices Magazine.

[2]  Hussein T. Mouftah,et al.  Low Power Family of Three-Valued Logic Circuits , 1985 .

[3]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[4]  T. Andoh,et al.  Design methodology for low-voltage MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[5]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[6]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[7]  Chenming Hu,et al.  A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[8]  Gary K. Yeap,et al.  Practical Low Power Digital VLSI Design , 1997 .

[9]  A. Srivastava,et al.  Design and Implementation of a Low Power Ternary Full Adder , 1996, VLSI Design.

[10]  H. Hara,et al.  50% active-power saving without speed degradation using standby power reduction (SPR) circuit , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[11]  Tzuen-Hsi Huang,et al.  Back-gate forward bias method for low-voltage CMOS digital circuits , 1996 .

[12]  J. Shott,et al.  A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[13]  Christer Svensson,et al.  Trading speed for low power by choice of supply and threshold voltages , 1993 .