Time to digital converter based on a 2-dimensions Vernier architecture

A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7bits TDC prototype realized in 65nm CMOS technology is presented. The chip has a resolution of 4.8ps with a power consumption of 1.7mW at a conversion rate of 50Msps.

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