论文信息 - Tracking Design Changes with Formal Machine - Checked Proof

Tracking Design Changes with Formal Machine - Checked Proof

Design are often modified for use in new circumstances. If formal proof is to be an acceptable verification methodology for industry, it must be capable of tracking design changes quickly. We describe our experiences formally verifying an implementation of an ATM network component, and on our subsequent verification of modified designs. Three of the designs verified are in use in a working network. They were designed and implemented with no consideration for formal methods. This case study gives an application of the difficulties in formally verifying a real design and of subsequently tracking design changes.

Paul Curzon | P. Curzon

[1] Kurt Stenzel,et al. Reuse of Proofs in Software Verification , 1993, FSTTCS.

[2] Robert S. Boyer,et al. A computational logic handbook , 1979, Perspectives in computing.

[3] J. Herbert,et al. Formal hardware verification methodology and its application to a network interface chip , 1986 .

[4] C. Q. Lee,et al. The Computer Journal , 1958, Nature.

[5] Derek McAuley,et al. Fairisle: An ATM Network for the Local Area , 1991, SIGCOMM.

[6] Paul Curzon,et al. Experiences formally verifying a network component , 1994, Proceedings of COMPASS'94 - 1994 IEEE 9th Annual Conference on Computer Assurance.

[7] Richard J. Boulton,et al. Experience with Embedding Hardware Description Languages in HOL , 1992, TPCD.

[8] Lauren Ruth Wiener. Digital woes - why we should not depend on software , 1993 .

[9] M. Gordon,et al. Introduction to HOL: a theorem proving environment for higher order logic , 1993 .

[10] J. Rushby,et al. Formal verification of an interactive consistency algorithm for the Draper FTP architecture under a hybrid fault model , 1994, Proceedings of COMPASS'94 - 1994 IEEE 9th Annual Conference on Computer Assurance.