论文信息 - The gate-bias influence for ESD characteristic of NMOS

The gate-bias influence for ESD characteristic of NMOS

The positive and negative gate-bias effect on ESD robustness of NMOS devices are analyzed respectively in this paper. The influence of gate-bias have been simulated by ISE TCAD and discussed. The simulation results indicate that the triggering voltage fell from 10.46V to 7.8V with the negative gate bias changed from 0V to −10V, and reduced from 10.46V to 5.92V with the positive gate bias changed from 0V to 3V. Under appropriate gate bias, the ESD protection devices can obtain lower Vt1 and higher Vt2. It gives benefit of triggering the large-dimension MOS uniformly, which can improve ESD robustness directly.

[1] Albert Wang. On-Chip Esd Protection for Integrated Circuits: An IC Design Perspective , 2002 .

[2] J.J. Liou,et al. TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications , 2007, IEEE Transactions on Electron Devices.

[3] S. Sze,et al. Physics of Semiconductor Devices: Sze/Physics , 2006 .

[4] Tung-Yang Chen,et al. ESD protection strategy for sub-quarter-micron CMOS technology: gate-driven design versus substrate-triggered design , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[5] Jian-Hsing Lee,et al. A Simple and Useful Layout Scheme to Achieve Uniform Current Distribution for Multi-Finger Silicided Grounded-Gate NMOS , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[6] Tung-Yang Chen,et al. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices , 2001 .

[7] S. Ramaswamy,et al. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations , 1996, Proceedings of International Reliability Physics Symposium.

[8] E. A. Amerasekera,et al. ESD in silicon integrated circuits , 1995 .