Hardware Design 2

Some microprocessors provide for dynamic bus sizing in which the peripheral or memory tells the central processing unit (CPU) the bus width. A typical device that implements dynamic bus sizing is the Motorola MC68HC16, which is a microcontroller with external bus capability. This chapter illustrates that the MC68HC16 uses a bus interface similar to the 68000 but with two acknowledge signals instead of one. An 8-bit peripheral or memory asserts -DSACK0 to terminate the cycle, and a 16-bit device asserts-DSACK1. To simplify the central processing unit (CPU) hardware, the MC68HC16 requires that 8-bit devices connect to data-bus lines 8 through 15, whereas 16-bit devices use all 16 data lines. Another feature implemented on the MC68HC16 is fast cycle termination. One problem with any bus structure that requires an acknowledge for each cycle is that for maximum speed, each peripheral must assert the acknowledge in a timely fashion. The normally-not-ready structure imposes a speed penalty in integral clocks for any peripheral that is slow to generate the acknowledge. Also, every peripheral must have logic to generate an acknowledge signal back to the CPU.