Memory BIST for on-chip monitoring of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array

We present a Built-in Self Test (BIST) methodology for on-chip failure analysis of via/contact voiding due to electromigration (EM) and stress-induced voiding (SIV) in SRAM cells. Our BIST system aims to detect wearout in faulty cells and identify the location of the failure in the cell. This enables more efficient physical failure analysis.

[1]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[2]  NaikSamir,et al.  Failure Analysis of High-Density CMOS SRAMs , 1993 .

[3]  Hans-Joachim Wunderlich,et al.  An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy , 2007, 12th IEEE European Test Symposium (ETS'07).

[4]  Shyue-Kung Lu,et al.  Efficient BISR Techniques for Embedded Memories Considering Cluster Faults , 2010, 13th Pacific Rim International Symposium on Dependable Computing (PRDC 2007).

[5]  Linda S. Milor,et al.  Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[7]  Sungho Kang,et al.  A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Linda S. Milor,et al.  Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[10]  Chang-Chih Chen,et al.  System-level modeling and microprocessor reliability analysis for backend wearout mechanisms , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  D. M. H. Walker,et al.  Improvement of SRAM-based failure analysis using calibrated Iddq testing , 1996, Proceedings of 14th VLSI Test Symposium.

[12]  Wojciech Maly,et al.  Yield-oriented computer-aided defect diagnosis , 1995 .

[13]  Wojciech Maly,et al.  Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing , 1993, IEEE Design & Test of Computers.

[14]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[15]  Arnaud Virazel,et al.  Resistive-open defects in embedded-SRAM core cells: analysis and march test solution , 2004, 13th Asian Test Symposium.

[16]  Linda Milor,et al.  NBTI resistant SRAM design , 2011, 2011 4th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI).