High Performance Arithmetic for DSP Systems

Digital Signal Processing, since its establishment as a discipline 30 years ago, has always received a great impetus from electronic technological advances. It often rides the crest of that wave and sometimes is responsible for pushing it.

[1]  Richard E. Blahut Fast Algorithms for Signal Processing and Error Control , 1985 .

[2]  Graham A. Jullien,et al.  VLSI implementations of number theoretic techniques in signal processing , 1993, Integr..

[3]  Graham A. Jullien,et al.  Area-time analysis of carry lookahead adders using enhanced multiple output domino logic , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[4]  Magdy A. Bayoumi,et al.  theta (logN) architectures for RNS arithmetic decoding , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[5]  W. K. Jenkins,et al.  Redundant residue number systems for error detection and correction in digital filters , 1980 .

[6]  W. C. Miller,et al.  Column Compression Multipliers For Signal Processing Applications , 1992, Workshop on VLSI Signal Processing.

[7]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.

[8]  N. Kingsbury,et al.  Digital filtering using logarithmic arithmetic , 1971 .

[9]  Bede Liu,et al.  A new hardware realization of digital filters , 1974 .

[10]  Graham A. Jullien,et al.  High-speed signal processing using systolic arrays over finite rings , 1988, IEEE J. Sel. Areas Commun..

[11]  John H. Cozzens,et al.  Computing the discrete Fourier transform using residue number systems in a ring of algebraic integers , 1985, IEEE Trans. Inf. Theory.

[12]  C. Svensson,et al.  Pushing the limits of standard CMOS , 1991, IEEE Spectrum.

[13]  Earl E. Swartzlander,et al.  The Sign/Logarithm Number System , 1975, IEEE Transactions on Computers.

[14]  Graham A. Jullien,et al.  New concepts for the design of carry lookahead adders , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[15]  Graham A. Jullien,et al.  A New Design Technique for Column Compression Multipliers , 1995, IEEE Trans. Computers.

[16]  R. Grondin,et al.  Dynamic computational blocks for bit-level systolic arrays , 1994 .

[17]  Graham A. Jullien,et al.  Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms , 1980, IEEE Transactions on Computers.

[18]  A. L. Fisher,et al.  Ultrafast compact 32-bit CMOS adders in multiple-output domino logic , 1989 .

[19]  Martine D. F. Schlag,et al.  Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip , 1990, IEEE Trans. Computers.

[20]  Graham A. Jullien,et al.  Analytical approach to sizing nFET chains , 1992 .

[21]  庄司 正一,et al.  CMOS digital circuit technology , 1988 .

[22]  Richard A. Games An algorithm for complex approximations in Z[e2{pi}i/8] , 1986, IEEE Trans. Inf. Theory.

[23]  David L. Pulfrey,et al.  Design procedures for differential cascode voltage switch circuits , 1986 .

[24]  Wayne P. Burleson,et al.  A VLSI design methodology for distributed arithmetic , 1991, J. VLSI Signal Process..

[25]  F. J. Taylor,et al.  A reduced-complexity finite field ALU , 1991 .

[26]  Lino. Del Pup The development and application of high-speed digital switching trees for regular arithmetic arrays. , 1991 .

[27]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[28]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[29]  Graham A. Jullien,et al.  A fast VLSI systolic array for large modulus residue addition , 1994, J. VLSI Signal Process..

[30]  Israel Koren Computer arithmetic algorithms , 1993 .

[31]  D. Birreck,et al.  VLSI architecture for a convolution-based DCT in residue arithmetic , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[32]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[33]  Graham A. Jullien,et al.  Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic , 1983, IEEE Transactions on Computers.

[34]  G A Jullien,et al.  Residue number system implementations of number theoretic transforms in complex residue rings , 1980 .

[35]  W K Jenkins Techniques for high-precision digital filtering with multiple microprocessors , 1986 .

[36]  Michael A. Soderstrand,et al.  Residue number system arithmetic: modern applications in digital signal processing , 1986 .

[37]  S. Bandyopadhyay,et al.  A low-overhead scheme for testing a bit-level finite ring systolic array , 1990, J. VLSI Signal Process..

[38]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[39]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[40]  Graham A. Jullien,et al.  On Modulus Replication for Residue Arithmetic Computations of Complex Inner Products , 1990, IEEE Trans. Computers.

[41]  Steven A. Tretter,et al.  Introduction to Discrete-Time Signal Processing , 1976 .

[42]  S.A. White,et al.  Applications of distributed arithmetic to digital signal processing: a tutorial review , 1989, IEEE ASSP Magazine.

[43]  Graham A. Jullien,et al.  Residue Number Scaling and Other Operations Using ROM Arrays , 1978, IEEE Transactions on Computers.

[44]  Charles M. Rader,et al.  Digital processing of signals , 1983 .

[45]  Earl E. Swartzlander,et al.  Estimating the power consumption of CMOS adders , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[46]  Peter R. Cappello,et al.  A VLSI layout for a pipelined Dadda multiplier , 1983, TOCS.

[47]  Thanos Stouraitis,et al.  Parallel Decomposition Of Complex Multipliers , 1988, Twenty-Second Asilomar Conference on Signals, Systems and Computers.

[48]  Graham A. Jullien,et al.  Flexible modulus residue number system for complex digital signal processing , 1991 .

[49]  James V. Krogmeier,et al.  The design of dual-mode complex signal processors based on quadratic modular number codes , 1987 .

[50]  Graham A. Jullien,et al.  Number Theoretic Techniques in Digital Signal Processing , 1991 .

[51]  Simon Haykin,et al.  Communication Systems , 1978 .

[52]  Christer Svensson,et al.  A unified single-phase clocking scheme for VLSI systems , 1990 .

[53]  Graham A. Jullien,et al.  Large Dynamic Range Computations over Small Finite Rings , 1994, IEEE Trans. Computers.

[54]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[55]  W.C. Miller,et al.  Current input TSPC latch for high speed, complex switching trees , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[56]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[57]  R. A. Games An algorithm for complex approximation in Z [e2πi/8] , 1986 .

[58]  Alan V. Oppenheim,et al.  Applications of digital signal processing , 1978 .

[59]  Graham A. Jullien,et al.  Complex digital signal processing over finite rings , 1987 .

[60]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[61]  Vassilis Paliouras,et al.  Systematic derivation of the processing element of a systolic array based on residue number system , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[62]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[63]  Norman R. Scott Computer Number Systems and Arithmetic , 1984 .