Impact of the RT-level architecture on the power performance of tunnel transistor circuits

Summary Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

[1]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[2]  Narayanan Vijaykrishnan,et al.  Steep slope devices: Enabling new architectural paradigms , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  C. Hu,et al.  Prospect of tunneling green transistor for 0.1V CMOS , 2010, 2010 International Electron Devices Meeting.

[4]  Dmitri E. Nikonov,et al.  Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits , 2015, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

[5]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[6]  A. Seabaugh,et al.  Tunnel Field-Effect Transistors: State-of-the-Art , 2014, IEEE Journal of the Electron Devices Society.

[7]  Massimo Alioto,et al.  Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Ian A. Young,et al.  Tunnel Field-Effect Transistors: Prospects and Challenges , 2015, IEEE Journal of the Electron Devices Society.

[9]  Juan Núñez,et al.  Comparison of TFETs and CMOS Using Optimal Design Points for Power–Speed Tradeoffs , 2017, IEEE Transactions on Nanotechnology.

[10]  Maria J. Avedillo,et al.  Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas , 2016, IEEE Transactions on Electron Devices.

[11]  Narayanan Vijaykrishnan,et al.  Modeling steep slope devices: From circuits to architectures , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Narayanan Vijaykrishnan,et al.  Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[13]  Qin Zhang,et al.  Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.

[14]  Massimo Alioto,et al.  Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I—Device–Circuit Interaction and Evaluation at Device Level , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Alan Seabaugh.  The Tunneling Transistor , 2013, IEEE Spectrum.

[16]  Narayanan Vijaykrishnan,et al.  An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[17]  Vinay Saripalli,et al.  III-V Tunnel FET Model 1.0.0 , 2014 .

[18]  Massoud Pedram,et al.  Power Aware Design Methodologies , 2002 .

[19]  J Avedillo Maria,et al.  Impact of pipeline in the power performance of tunnel transistor circuits , 2016 .

[20]  S. Datta,et al.  Tunnel Transistors for Low Power Logic , 2013, 2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[21]  P. Ajayan,et al.  A subthermionic tunnel field-effect transistor with an atomically thin channel , 2015, Nature.