High critical electric field of thin silicon film and its realization in SOI high voltage devices

Taking threshold energy epsiv<sub>T</sub> into accounting for electron multiplying, the formula of silicon critical electric field E<sub>S,C</sub> is given as a function of silicon film thickness t<sub>s</sub> from an effective ionization rate alpha<sub>eff</sub>. E<sub>S,C</sub> is increasing with the decreasing of t<sub>s</sub> especially at thinner t<sub>s</sub>. 2-D simulative and some experimental results as well as the comparing with several other familiar expressions of electric field proved the proposed E<sub>S,C</sub> is valid for both thick and thin silicon film. Thin silicon film with high E<sub>S,C</sub> can be used to enhance dielectric field E<sub>I</sub> and increase vertical breakdown voltage V<sub>B,V</sub> of SOI high voltage devices. A high voltage SOI device with 80 nm silicon layer and 0.4mum dielectric layer is designed. A high E<sub>S,C</sub> of 134V/mum is obtained, which makes E<sub>I</sub> and V<sub>B,V</sub> reach to 416 V/mum and 178 V, respectively.

[1]  R. A. Logan,et al.  Internal Field Emission at Narrow Silicon and Germanium p-n Junctions , 1960 .

[2]  Holger Kapels,et al.  Dielectric charge traps. A new structure element for power devices , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[3]  S. L. Miller.  Ionization Rates for Holes and Electrons in Silicon , 1957 .

[4]  H. Funaki,et al.  New high voltage SOI device structure eliminating substrate bias effects , 1996, International Electron Devices Meeting. Technical Digest.

[5]  Akio Nakagawa,et al.  New 1200 V MOSFET structure on SOI with SIPOS shielding layer , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[6]  R. V. Overstraeten,et al.  Measurement of the ionization rates in diffused silicon p-n junctions , 1970 .

[7]  Zhaoji Li,et al.  New thin-film power MOSFETs with a buried oxide double step structure , 2006 .

[8]  Bo Zhang,et al.  New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI , 2008, IEEE Transactions on Electron Devices.

[9]  Bo Zhang,et al.  A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer , 2007 .

[10]  Shengdong Zhang,et al.  Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices , 1999 .

[11]  S. Mukherjee,et al.  Realization of high breakdown voltage (>700 V) in thin SOI devices , 1991, [1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs.

[12]  W. Fulop,et al.  Calculation of avalanche breakdown voltages of silicon p-n junctions , 1967 .

[13]  S. Sze,et al.  AVALANCHE BREAKDOWN VOLTAGES OF ABRUPT AND LINEARLY GRADED p‐n JUNCTIONS IN Ge, Si, GaAs, AND GaP , 1966 .

[14]  M. Qiao,et al.  The Rule of Field Enhancement for Buried Dielectric Layer of SOI High Voltage Devices , 2007, 2007 International Conference on Communications, Circuits and Systems.

[15]  Bo Zhang,et al.  Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator , 2009, IEEE Transactions on Electron Devices.

[16]  Akio Nakagawa,et al.  Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film , 1991 .