The use of carry-save representation in joint module selection and retiming

Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In implementing high-speed circuits, the use of carry-save signal representation is also a powerful technique to optimize the implementation cost and the speed of arithmetic circuits. This paper is the first to combine these two techniques to solve the joint module selection and retiming problem while allowing the use of carry-save representation. To solve this problem efficiently, we first propose a mixedreprcsentation data-flow graph (MFG) that allows signals to be expressed in carry-save representation. We also propose techniques to ac:curately model the costs associated with different signal representiations. In addition, we propose a solution-space pruning technique that significantly reduces the run-time of our algorithm. Our algorithm, by allowing carry-save representation, can produce a wider range of solutions. In our experiments, our fastest implementation is 28% faster and our smallest implementation is 47% smaller, in comparison to solutions obtained using the previously known joint module selection and retiming technique.