Using active cache to solve the bottleneck of bus in the parallel Radar signal process system

Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs

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