Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs

Advances in semiconductor technology permit increasingly complex applications to be realized using programmable systems-on-chips (SOCs). Furthermore, shrinking time-to-market demands, coupled with the need for product versioning through software modification of SOC platforms, have led to a significant increase in the software content of these SOCs. However, designer productivity is greatly hampered by the lack of automated software generation tools for the exploration and evaluation of different architectural configurations. Traditional hardware-software codesign flows do not support effective exploration and customization of the embedded processors used in programmable SOCs. The inherently application-specific nature of embedded processors and the stringent area, power, and performance constraints in embedded systems design critically require a fast and automated architecture exploration methodology. Architecture description language (ADL)-Driven design space exploration and software toolkit generation strategies present a viable solution to this problem, providing a systematic mechanism for a top-down design and validation of complex systems. The heart of this approach lies in the ability to automatically generate a software toolkit that includes an architecture-sensitive compiler, a cycle-accurate simulator, assembler, debugger, and verification/validation tools. This article illustrates a software toolkit generation methodology using the EXPRESSION ADL. Our exploration studies demonstrate the need for and usefulness of this approach, using as an example the problem of compiler-in-the-loop design space exploration of reduced instruction-set embedded processor architectures.

[1]  Rainer Leupers,et al.  Retargetable Code Generation Based on Structural Processor Description , 1998, Des. Autom. Embed. Syst..

[2]  Nikil D. Dutt,et al.  Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications , 2003, Des. Autom. Embed. Syst..

[3]  Aviral Shrivastava,et al.  An efficient compiler technique for code size reduction using reduced bit-width ISAs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[4]  Aviral Shrivastava,et al.  Compilation framework for code size reduction using reduced bit-width ISAs (rISAs) , 2006, TODE.

[5]  Aviral Shrivastava,et al.  PBExplore: a framework for compiler-in-the-loop exploration of partial bypassing in embedded processors , 2005, Design, Automation and Test in Europe.

[6]  Philip M Evans The sparc architecture manual , 1991 .

[7]  Aviral Shrivastava,et al.  Automatic generation of operation tables for fast exploration of bypasses in embedded processors , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[8]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[9]  Nikil D. Dutt,et al.  A retargetable framework for instruction-set architecture simulation , 2006, TECS.

[10]  Srinivas Devadas,et al.  ISDL: an instruction set description language for retargetability , 1997, DAC.

[11]  Maria Freericks,et al.  The nml machine description formalism , 1991 .

[12]  Aviral Shrivastava,et al.  Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA) , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[13]  Heinrich Meyr,et al.  LISA-machine description language and generic machine model for HW/SW co-design , 1996, VLSI Signal Processing, IX.

[14]  Chuck Siska,et al.  A processor description language supporting retargetable multi-pipeline DSP program development tools , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

[15]  Nikil D. Dutt,et al.  Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models , 2003, 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings..

[16]  Hiroyuki Tomiyama,et al.  Architecture Description Languages for Systems-on-Chip Design , 1999 .

[17]  Nikil D. Dutt,et al.  Graph-based functional test program generation for pipelined processors , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[18]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[19]  Nikil D. Dutt,et al.  Instruction set compiled simulation: a technique for fast and flexible instruction set simulation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[20]  Srinivas Devadas,et al.  A methodology for accurate performance evaluation in architecture exploration , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[21]  Nikil D. Dutt,et al.  An efficient retargetable framework for instruction-set simulation , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[22]  Kevin D. Kissell MIPS16: High-density MIPS for the Embedded Market1 , 1997 .

[23]  Prabhat Mishra,et al.  Architecture description languages for programmable embedded systems , 2005 .

[24]  Aviral Shrivastava,et al.  Operation tables for scheduling in the presence of incomplete bypassing , 2004, CODES+ISSS '04.

[25]  Heinrich Meyr,et al.  Architecture implementation using the machine description language LISA , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[26]  Heinrich Meyr,et al.  Retargetable compiled simulation of embedded processors using a machine description language , 2000, TODE.

[27]  Paul C. Clements,et al.  A survey of architecture description languages , 1996, Proceedings of the 8th International Workshop on Software Specification and Design.

[28]  Nikil D. Dutt,et al.  Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC] , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[29]  Nikil D. Dutt,et al.  Functional verification of programmable embedded architectures - a top-down approach , 2005 .

[30]  Keith D. Cooper,et al.  Improvements to graph coloring register allocation , 1994, TOPL.

[31]  Aviral Shrivastava,et al.  A customizable compiler framework for embedded systems , 2001 .

[32]  Nikil D. Dutt,et al.  Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[33]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[34]  Mario Barbacci,et al.  Instruction set processor specifications (ISPS): The notation and its applications , 1981, IEEE Transactions on Computers.