FPGA implementation of synchronous section-carry based carry look-ahead adders

It is common knowledge that carry look-ahead adders constitute a high-speed method of performing binary addition in logarithmic time. As an improvement, in this paper, FPGA based realization of high-speed carry look-ahead adders based on the concept of section-carry is discussed. Three kinds of carry look-ahead adder architectures viz. Type 1, Type 2, Mixed are presented. In comparison with conventional carry look-ahead adders of sizes 16, 32 and 64-bits, the proposed section-carry based carry look-ahead adders report improvements in speed of 14.9%, 12.1% and 13% for Type 1, Type 2 and Mixed topologies respectively, for simulations targeting a 90nm FPGA device.

[1]  P. Balasubramanian,et al.  Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic , 2013, J. Circuits Syst. Comput..

[2]  Sung-Mo Kang,et al.  A 32-bit carry lookahead adder using dual-path all-N logic , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Soo-Ik Chae,et al.  A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems , 1999 .

[4]  José F. López,et al.  Pipelined GaAs carry lookahead adder , 1998 .

[5]  A. H. Shaltoot,et al.  Memristor based carry lookahead adder architectures , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

[6]  Stephen H. Unger,et al.  Self-Timed Carry-Lookahead Adders , 2000, IEEE Trans. Computers.

[7]  Jin-Hau Kuo,et al.  A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit , 1993 .

[8]  Chua-Chin Wang,et al.  A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Roberto Saletti,et al.  Ultralow-power adiabatic circuit semi-custom design , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Yusuf Leblebici,et al.  Design aspects of carry lookahead adders with vertically-stacked nanowire transistors , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[11]  G. A. Ruiz.  New static multi-output carry lookahead CMOS adders , 1997 .

[12]  Borivoje Nikolic,et al.  Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example , 2009, IEEE Journal of Solid-State Circuits.

[13]  E. Swartzlander,et al.  Adder Designs and Analyses for Quantum-Dot Cellular Automata , 2007, IEEE Transactions on Nanotechnology.