Optimizing System-on-Chip Performance Using AI and SDN: Approaches and Challenges
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[1] Yang Ni,et al. DARL: Distributed Reconfigurable Accelerator for Hyperdimensional Reinforcement Learning , 2022, ICCAD.
[2] Y. Shu,et al. mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips , 2022, IEEE Embedded Systems Letters.
[3] A.J. de Geus. Catalyzing the Impossible: Silicon, Software, and Smarts for the SysMoore Era , 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).
[4] H. Wong. On the CMOS Device Downsizing, More Moore, More than Moore, and More-than-Moore for More Moore , 2021, 2021 IEEE 32nd International Conference on Microelectronics (MIEL).
[5] Alaa Eddin Alchalabi,et al. Toward integrating software defined networks with the Internet of Things: a review , 2021, Cluster Computing.
[6] Ryan Liu,et al. AI Compute Chip from Enflame , 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).
[7] J. L. Vázquez-Avila,et al. A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities , 2021, Micromachines.
[8] Soon Ee Ong,et al. Artificial Neuron Hardware IP Verification , 2020, 2020 IEEE 29th Asian Test Symposium (ATS).
[9] W. Fang,et al. A Real-time Emotion Recognition System Based on an AI System-On-Chip Design , 2020, 2020 International SoC Design Conference (ISOCC).
[10] Wai-Chi Fang,et al. An Edge AI System-on-Chip Design with Customized Convolutional-Neural-Network Architecture for Real-time EEG-Based Affective Computing System , 2019, 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS).
[11] Mladen Bozanic,et al. Systems-Level Packaging for Millimeter-Wave Transceivers , 2019, Smart Sensors, Measurement and Instrumentation.
[12] Soultana Ellinidou,et al. A SDN solution for system-on-chip world , 2018, 2018 Fifth International Conference on Software Defined Systems (SDS).
[13] Jonatan Ostrometzky,et al. SDNoC: Software defined network on a chip , 2017, Microprocess. Microsystems.
[14] Andrew B. Kahng,et al. Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning , 2017, ISPD.
[15] Xuan Zeng,et al. Machine learning and pattern matching in physical design , 2015, The 20th Asia and South Pacific Design Automation Conference.
[16] Yaroslav M. Krainyk,et al. Information Technology for Configuration of System-on-Chip in Cloud Environment , 2020, ICTERI.
[17] Wei Gao,et al. Customized High Performance and Energy Efficient Communication Networks for AI Chips , 2019, IEEE Access.
[18] Saurabh Sinha,et al. Traditional Approach: System-on-Chip , 2019, Smart Sensors, Measurement and Instrumentation.
[19] Darron May. Improving Verification Predictability and Efficiency Using Big Data , 2017 .
[20] Sao-Jie Chen,et al. Networks on Chips: Structure and Design Methodologies , 2012, J. Electr. Comput. Eng..
[21] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.