An efficient scheduling mechanism with flow-based packet reordering in a high-speed network processor

In most network processors (NP), multiple CPU cores are employed to exploit packet level parallelism, where high processing resource utilization and within-flow packet order preservation are two fundamental design targets. However, while many researches are only focused on the first one, the second has not been solved perfectly. In this paper, a high-speed NP architecture is proposed to handle both of the two issues simultaneously, where a centralized state controller with hardware flow chains is employed to schedule the CPU cores fairly and to transmit the packets orderly. We also introduce local memory to increase CPU utilization as well as to store packets that can't be sent out immediately due to flow constraints. We implement the NP prototype with an FPGA, upon which a series of experiments are carried out, and the results indicate that it can achieve both of the two goals perfectly.