Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology

One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to attach them to a next level die by means of thermocompression bonding. This results in induced stresses in the silicon due to the large CTE disparity between copper and silicon, and also from the force applied during thermocompression bonding. These stresses can have an impact on the performance of the transistors and may as well result in die fracture. This paper studies these stresses through Finite Element modeling. We found that the keep-away- zone of the transistors from the copper via where transistor performance is impacted by the through-Si interconnect proximity, is proportional to the via diameter. The bonding temperature is found to be the main cause for the induced stresses during the thermocompression bonding process. The induced stresses in silicon decrease with decreasing the silicon thickness.

[1]  Charles S. Smith.  Piezoresistance Effect in Germanium and Silicon , 1954 .

[2]  IEEE Spectrum , 2022 .

[3]  E. Beyne,et al.  3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias , 2006, 2006 International Electron Devices Meeting.

[4]  K. Matsui,et al.  Optimization for chip stack in 3-D packaging , 2005, IEEE Transactions on Advanced Packaging.

[5]  S. Thompson,et al.  Uniaxial-process-induced strained-Si: extending the CMOS roadmap , 2006, IEEE Transactions on Electron Devices.

[6]  A. Moll,et al.  Thermo-mechanical characterization of copper through-wafer interconnects , 2006, 56th Electronic Components and Technology Conference 2006.

[7]  Ulrich Ramacher,et al.  3D chip stack technology using through-chip interconnects , 2005, IEEE Design & Test of Computers.

[8]  M. Karnezos,et al.  3D packaging: where all technologies come together , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

[9]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[10]  Yozo Kanda,et al.  Nonlinear piezoresistance effects in silicon , 1993 .

[11]  M. Tomisaka,et al.  Development of advanced 3D chip stacking technology with ultra-fine interconnection , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[12]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[13]  H. Goldstein.  Packages go vertical , 2001 .

[14]  Kazumasa Tanida,et al.  Ultra-high-density 3D chip stacking technology , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..