Symbolic inner loop parallelisation for massively parallel processor arrays
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[1] Narayanan Vijaykrishnan,et al. Run-time adaption for highly-complex multi-core systems , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[2] Yves Robert,et al. Affine-by-Statement Scheduling of Uniform and Affine Loop Nests over Parametric , 1995, J. Parallel Distributed Comput..
[3] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[4] Jürgen Teich,et al. Symbolic Mapping of Loop Programs onto Processor Arrays , 2014, J. Signal Process. Syst..
[5] Uday Bondhugula,et al. Automatic mapping of nested loops to FPGAS , 2007, PPoPP.
[6] Karl-Heinz Zimmermann,et al. Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming , 2001, FME 2001.
[7] Jürgen Teich,et al. Resource-aware programming and simulation of MPSoC architectures through extension of X10 , 2011, SCOPES.
[8] Uwe Eckhardt,et al. Scheduling in co-partitioned array architectures , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.
[9] I. Radivojevic,et al. Symbolic Scheduling Techniques , 1995, IEICE Trans. Inf. Syst..
[10] Dan I. Moldovan,et al. Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays , 1986, IEEE Transactions on Computers.
[11] Lothar Thiele,et al. On the design of piecewise regular processor arrays , 1989, IEEE International Symposium on Circuits and Systems,.
[12] Frank Hannig,et al. Invasive Tightly-Coupled Processor Arrays , 2014, ACM Trans. Embed. Comput. Syst..
[13] Jürgen Teich,et al. Invasive Computing: An Overview , 2011, Multiprocessor System-on-Chip.
[14] Jürgen Teich,et al. Symbolic parallelization of loop programs for massively parallel processor arrays , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.
[15] Yves Robert,et al. Linear scheduling is close to optimality , 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.
[16] Jürgen Teich,et al. Invasive Algorithms and Architectures Invasive Algorithmen und Architekturen , 2008, it Inf. Technol..
[17] Karl-Heinz Zimmermann,et al. A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP , 1997, J. VLSI Signal Process..
[18] S. Mahlke,et al. Multicore compilation strategies and challenges , 2009, IEEE Signal Processing Magazine.
[19] Jürgen Teich,et al. A highly parameterizable parallel processor array architecture , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[20] B. Ramakrishna Rau,et al. A Constructive Solution to the Juggling Problem in Systolic Array Synthesis , 2000 .
[21] Oscar H. Ibarra,et al. On symbolic scheduling and parallel complexity of loops , 1995, Proceedings.Seventh IEEE Symposium on Parallel and Distributed Processing.
[22] Frédéric Vivien,et al. A constructive solution to the juggling problem in processor array synthesis , 2000, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000.
[23] Leslie Lamport,et al. The parallel execution of DO loops , 1974, CACM.